1. Field of the Invention
This invention relates to a circuit substrate device, on which a pattern conductor has been formed properly, a method for producing the same, a semiconductor device, and a method for producing the same. This application claims priority of Japanese Patent Application No. 2002-105549, filed on, 2002, the entirety of which is incorporated by reference herein.
2. Description of Related Art
Recently, there is raised a demand for a technique of mounting functional elements, such as semiconductor chips, on e.g., a substrate, to a high density, for keeping up to the reduction in size and thickness, and to the advanced and diversified functions of electronic equipment. These functional elements are mounted on the substrate in the form of a mold package, such as QFP (Quad Flat Package) or a SOP (Small Outline Package), a package of a smaller size, such as BGA (Ball Grid Array) or CSP (Chip Scale Package), or MCM (multi-chip module), for mounting plural semiconductor chips.
In the mounting configuration for the functional elements, such as BGA, CSP or MCM, a semiconductor chip is mounted on a wiring substrate by pair-chip mounting, and an electrode land is arranged on a surface of the wiring substrate opposite to the surface thereof mounting the wiring substrate. The electrode land is used as a connection terminal to a motherboard.
As a substrate for mounting the semiconductor chip, a wiring substrate of an organic material, such as a glass epoxy substrate or a polyimide substrate, or a wiring substrate of an inorganic material, such as ceramics substrate. In particular, as the wiring substrate of an organic material, used for mounting a semiconductor chip having a large number of connecting terminals, such as connection pins, or used for MCM mounting, a multi-layer wiring substrate 100, or a so-called FR (flame-retardant) substrate, is used, as shown in FIG. 1. This multi-layer wiring substrate 100 includes a via-hole 102, with a diameter on the order of 50 μm, for interconnecting multi-layered pattern conductors 101 by for example laser processing. With this multi-layer wiring substrate 100, the line width of the pattern conductor 101 can be as fine as approximately 100 μm.
However, with the above-described multi-layer wiring substrate 100, there is raised, in keeping up with the tendency towards an increased number of the semiconductor chips and a decreased pitch between the connection pins, a demand for increasing the density of the pattern conductors 101 on the surface of the multi-layered pattern conductors 101 mounting the semiconductor chip. Since the number of the lines in the semiconductor chip for MCM mounting in near future amounts to several thousands or to several tens of thousands, it is required to raise the density of the pattern conductors 101 further.
If, in the present multi-layer wiring substrate 100, plural semiconductor chips are connected to a large number of conductor patterns, it becomes necessary to increase the mounting area or to increase the number of layers of the pattern conductors 101. With the multi-layer wiring substrate 100, the line length of the pattern conductors 101 in increased, while the number of the via-holes 102 is increased with increasing numbers of the via-holes, with the consequence that the numbers of the C, L and R components in the pattern conductors 101 may be increased to deteriorate electrical characteristics.
Moreover, in producing the multi-layer wiring substrate 100, the manufacturing process may be complex with the increasing number of the layers of the pattern conductors 101 to increase the production time or to lower the production efficiency.
On the other hand, a wiring substrate of an inorganic material, such as Si substrates or glass substrates, may also be used in place of the multi-layer wiring substrate 100. Since these Si or glass substrates are superior in surface smoothness and in thermal resistance, pattern conductors may be formed on its mounting surface for semiconductor chips, by employing for example the thin film forming technique, to a finer line width than is possible with the above-described multi-layer wiring substrate 100.
However, with the Si substrate or the glass substrate, it is difficult to form e.g., via-holes, such that electrode lands, operating as connection terminals for a motherboard, cannot be formed on a surface on the opposite side of the mounting surface for the semiconductor chip, with the consequence that these substrates cannot be used as mounting substrates for the semiconductor chips.